1. Field of the Invention
The present invention relates generally to digital computer systems, and more specifically to techniques for testing memory locations within such computer systems.
2. Description of the Prior Art
In digital computer systems, testing of memory included in such systems is important. In general, memory testing is performed prior to using the computer system. However, it is possible to test memory while the system is operating, if desired.
Memory testing becomes more important as computer systems grow to include larger memories, since the chances of a memory error increase as the memory size increases. Many recent systems include error correcting code (ECC) instead of the simple parity bits included in older and smaller systems. Use of ECC allows the correction of soft errors during execution of the system, and increased reliability in detecting multi-bit errors.
Reliability of a system can be increased by checking address parity as well as parity of the data. Address parity checking allows detection and isolation of address-related faults.
It would be desirable to provide a method for determining the location of a memory error, and identify whether such an error is data, ECC data, or address related.